These moves show where the real AI infrastructure bottlenecks now sit. Accelerator designs advance every year, but each new generation needs more advanced packaging, more memory bandwidth, faster optical links and far more power per rack. The pace of AI capacity growth is increasingly set by the slowest of these inputs.
Where AI Infrastructure Bottlenecks Sit Today
The constraints run along the whole path from silicon to grid. Each one has its own lead times, suppliers and investment cycle, which is why they rarely ease at the same time.
| Bottleneck | Why it matters | October response |
| Substrates | Carry the complex wiring that connects AI chip assemblies | IBIDEN, SEMCO and Unimicron to raise output 2.5x over three years |
| Interposers and advanced packaging | Join compute dies and HBM memory at high bandwidth | GlobalFoundries and TSMC $2B deal; Amkor capacity up 300%+ by end-2028 |
| Testing | Every complex package must be validated before shipping | KYEC US facilities with $1.1B advance; testing capacity to double 2026 to 2027 |
| Optical engines | Connect ever-larger clusters at lower power | SPIL optical engine capacity up 15x by mid-2027 |
| Power | Grid connections take years and capacity is scarce | Behind-the-meter generation; siting near hydro; renewable commitments |
| Community and permits | Energy, water and land use face growing scrutiny | Community investment programmes; regulatory reviews in several markets |
Advanced Packaging: The Hidden AI Infrastructure Bottleneck
Modern AI accelerators are not single chips. They combine compute dies and stacks of high-bandwidth memory on silicon interposers and substrates that allow data to move between them at enormous speed. AMD‘s Instinct MI355X, for example, pairs its compute with 288 GB of HBM3E memory and 8 TB/s of memory bandwidth. Building these assemblies requires specialised packaging capacity, advanced substrates and extensive testing, all of which have struggled to keep pace with demand.
NVIDIA‘s October announcements set out how much capacity it is securing. It signed agreements with IBIDEN, Samsung Electro-Mechanics and Unimicron to raise substrate output 2.5 times over three years. Amkor will expand interposer wafer packaging capacity in South Korea by more than 300% by the end of 2028, under a $1.3 billion agreement that also covers substrates, testing and optical engines. KYEC will add new US testing facilities backed by a $1.1 billion capacity reservation advance, and NVIDIA expects total semiconductor testing capacity for its products to double from 2026 to 2027. IBIDEN’s Ono plant in Japan is due to begin ramping additional capacity from the first quarter of 2028.
Capacity is also being added closer to end markets. The GlobalFoundries and TSMC agreement will see silicon interposers produced at GlobalFoundries’ facility in Malta, New York, with volume production expected in the first half of 2028. Software is part of the answer too: Dassault Systèmes is positioning its platform to connect silicon design with advanced packaging for chiplets and HBM, reducing the time needed to bring multi-die systems to production.
Capacity Reservations Reshape the AI Infrastructure Supply Chain
A notable feature of these deals is who is paying. Rather than waiting for suppliers to invest, the largest chip designers are funding capacity in advance through prepayments and reservation agreements, such as NVIDIA’s multibillion-dollar advance to IBIDEN for packaging substrates. This approach gives suppliers the confidence to build expensive new lines and gives the buyer priority access when they come online.
The result is a supply chain increasingly organised around long-term commitments. For smaller chip designers, hyperscalers developing their own accelerators and sovereign programmes, securing packaging, substrate and testing capacity is becoming as strategic as securing wafer supply. Government policy is reinforcing this: Japan will fund $20 billion for two new fabs at GlobalFoundries’ New York campus under a US and Japan trade arrangement, and TSMC is evaluating a further multibillion-dollar campus in Texas.
Optics: The Next AI Infrastructure Bottleneck
As AI clusters grow to tens or hundreds of thousands of accelerators, the links between them become a constraint in their own right. Co-packaged optics, which place optical engines alongside switch and compute silicon, promise lower power and higher bandwidth than pluggable modules, but require new manufacturing capacity. SPIL plans a 15-fold increase in optical engine capacity for co-packaged optics by mid-2027, and to double it again by the end of 2028. At the OCP Global Summit, NVIDIA and Cisco introduced the USFP optical standard targeting 400 Gbps per lane, while Meta is adopting 102.4 Tbps Spectrum-6 Ethernet switches to scale beyond 100,000 GPUs.
Power Is the Defining AI Infrastructure Bottleneck
Packaging constraints are severe but solvable with investment and time. Power is harder. Grid connections for large AI campuses can take years to secure, and in many regions available capacity is already committed. Digital Realty’s proposed Kokomo campus illustrates the scale: a three-building site targeting around 1 GW of IT capacity by 2033, expected to draw around 1.5 GW from Duke Energy, with grid agreements still pending.
Developers are responding in three ways:
- Generating on site: Crusoe’s $700 million facility from Neuberger Specialty Finance funds behind-the-meter gas generators for its AI data centres, part of a platform with more than 6 GW of gross AI capacity under contract.
- Building where power is available: Crusoe and Araico are developing a facility next to the Itaipú substation in Paraguay, powered by hydroelectric energy, starting at 106 MW of IT capacity in mid-2027 with options to expand to around 280 MW.
- Committing to renewable supply: Cortex DC plans 2 GW of AI-ready capacity across India and has committed to source 51% of its energy from renewables.
Making Every Megawatt Count Against AI Infrastructure Bottlenecks
When power is the limiting factor, efficiency becomes capacity. Average rack loads have roughly doubled from about 12 kW in 2024 to 26 kW in 2026, as noted in our September Digital Infrastructure Insights, and rack designs now reach 250 kW with liquid cooling. Liquid cooling allows more compute per square metre and per megawatt, and closed-loop designs with dry coolers can largely eliminate facility cooling water use.
Software is helping to stretch supply further. NVIDIA says its DSX MaxLPS power management can deliver up to 30% lower power for the same token output, while DSX Flex coordinates workload power with grid conditions. The new OCP Grid Resilience Specification, published by NVIDIA, Google, Meta and Microsoft, targets recovery from grid events in under two seconds, making large AI loads better behaved on the grid and easier for utilities to accommodate.
Community and Regulatory AI Infrastructure Bottlenecks
Beyond engineering, AI data centres face growing scrutiny over electricity, water and land use. Authorities from New York and Ireland to Denmark and Thailand are introducing new policies, construction restrictions and grid connection requirements. Indonesia and Thailand have paused some major data centre developments for regulatory review, and Malaysia is addressing rising electricity demand. In South Korea, a major semiconductor cluster has faced power and water delays. Developers are responding with community investment: AWS has committed more than $1 billion over five years to programmes in communities hosting its US data centres, and Digital Realty plans to fund local water infrastructure upgrades and cap noise at its Kokomo site.
What AI Infrastructure Bottlenecks Mean for Telcos and Enterprises
For telecom operators, power scarcity creates both a challenge and an opportunity. Sites with existing grid connections and spare power become more valuable, and distributed inference at edge and regional sites can spread AI demand across many smaller power connections rather than concentrating it in a few giant campuses. For enterprises, the lesson is to plan AI capacity with realistic lead times, treat power availability as a first-order site selection criterion, and favour efficient, liquid-ready designs that deliver more output per megawatt.
AI Infrastructure Bottleneck Milestones to Watch
Much of the new capacity announced in October will take two years or more to come online, so the timing of each step matters for anyone planning AI deployments. These milestones show when the main AI infrastructure bottlenecks should start to ease:
- Early 2027: first partner deliveries of factory-built AI pods that shorten on-site deployment.
- Mid-2027: SPIL’s 15-fold optical engine expansion and first service at Crusoe’s Paraguay facility.
- First quarter of 2028: additional substrate capacity ramps at IBIDEN’s Ono plant.
- First half of 2028: volume production of silicon interposers under the GlobalFoundries and TSMC agreement.
- End of 2028: Amkor’s more than 300% expansion of interposer packaging capacity in South Korea.
The industry is investing heavily to clear these constraints, and the packaging bottleneck in particular should ease as new capacity arrives through 2027 and 2028. Power is likely to remain the defining limit for longer. The organisations that secure grid capacity, build efficiently and plan around realistic lead times will be the ones able to turn the next generations of AI hardware into working capacity.
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